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VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper explores the recovery and rate capacity effect for batteries used in embedded systems. It describes the prominent battery models with their advantages and drawbacks. It...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
In this paper, we have studied and compared the RF performance metrics, unity gain frequency (ft) and Noise Figure (NF), of the devices with channel engineering consisting of halo...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...