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DGCI
2005
Springer
14 years 1 months ago
Increasing Interconnection Network Connectivity for Reducing Operator Complexity in Asynchronous Vision Systems
Due to the restriction of SIMD mode to local operations in VLSI massively parallel vision chips, using programmable connections and asynchronous communications are key ingredients ...
Valentin Gies, Thierry M. Bernard
PATMOS
2005
Springer
14 years 1 months ago
Efficient Simulation of Power/Ground Networks with Package and Vias
As the number of metal layers and the frequency of VLSI continue to increase, the voltage droop on both the package and vias is becoming more pronounced. This paper analyzes the nu...
Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Ta...
SAMOS
2005
Springer
14 years 1 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Process variation robust clock tree routing
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
Wai-Ching Douglas Lam, Cheng-Kok Koh
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Register placement for low power clock network
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...