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    ISVLSI
    2005
    IEEE
    95views VLSI» more  ISVLSI 2005»
    System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures
    14 years 1 months ago
    System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures
    Download  www.princeton.edu
    Vijaykumar Ramamurthi, Jason McCollum, Christopher...
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    ISVLSI
    2005
    IEEE
    102views VLSI» more  ISVLSI 2005»
    Bi-Direction Synthesis for Reversible Circuits
    14 years 1 months ago
    Bi-Direction Synthesis for Reversible Circuits
    Download  web.cecs.pdx.edu
    Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek...
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    ISCAS
    2005
    IEEE
    126views Hardware» more  ISCAS 2005»
    Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT
    14 years 1 months ago
    Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT
    Download  video.ee.ntu.edu.tw
    Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, C...
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    GLVLSI
    2005
    IEEE
    122views VLSI» more  GLVLSI 2005»
    PIM lite: a multithreaded processor-in-memory prototype
    14 years 1 months ago
    PIM lite: a multithreaded processor-in-memory prototype
    Download  www.cse.nd.edu
    Abstract— PIM Lite is a processor-in-memory prototype implemented in a 0.18 micron logic process. PIM Lite provides a complete working demonstration of a minimal-state, lightweig...
    Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinz...
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    GLVLSI
    2005
    IEEE
    103views VLSI» more  GLVLSI 2005»
    Causal probabilistic input dependency learning for switching model in VLSI circuits
    14 years 1 months ago
    Causal probabilistic input dependency learning for switching model in VLSI circuits
    Download  www.eng.usf.edu
    Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active ...
    Nirmal Ramalingam, Sanjukta Bhanja
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