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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 7 months ago
Rapid Embedded Hardware/Software System Generation
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya,...
VLSID
2005
IEEE
118views VLSI» more  VLSID 2005»
14 years 7 months ago
Battery Model for Embedded Systems
This paper explores the recovery and rate capacity effect for batteries used in embedded systems. It describes the prominent battery models with their advantages and drawbacks. It...
Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas ...
VLSID
2005
IEEE
98views VLSI» more  VLSID 2005»
14 years 7 months ago
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 7 months ago
Implementing LDPC Decoding on Network-on-Chip
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
Theo Theocharides, Greg M. Link, Narayanan Vijaykr...
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
14 years 7 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan