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    VLSISP
    2002
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    A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
    13 years 11 months ago
    A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
    Download  utdallas.edu
    3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. Th...
    Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander ...
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