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    Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
    13 years 6 months ago
    Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
    Download  www.gtcad.gatech.edu
    —Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
    Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
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