Sciweavers

ICPP
2007
IEEE
14 years 5 months ago
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
DAC
2000
ACM
15 years 12 days ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...