Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...