Sciweavers

TPHOL
2009
IEEE
14 years 5 months ago
Some Domain Theory and Denotational Semantics in Coq
Abstract. We present a Coq formalization of constructive ω-cpos (extending earlier work by Paulin-Mohring) up to and including the inverselimit construction of solutions to mixed-...
Nick Benton, Andrew Kennedy, Carsten Varming
TPHOL
2009
IEEE
14 years 5 months ago
Types, Maps and Separation Logic
Abstract. This paper presents a separation-logic framework for reasoning about low-level C code in the presence of virtual memory. We describe ract, generic Isabelle/HOL framework ...
Rafal Kolanski, Gerwin Klein
TPHOL
2009
IEEE
14 years 5 months ago
Formalising FinFuns - Generating Code for Functions as Data from Isabelle/HOL
Abstract. FinFuns are total functions that are constant except for a finite set of points, i.e. a generalisation of finite maps. We formalise them in Isabelle/HOL and present how...
Andreas Lochbihler
ISMVL
2009
IEEE
88views Hardware» more  ISMVL 2009»
14 years 5 months ago
Minimal Coverings of Maximal Partial Clones
A partial function f on an k-element set Ek is a partial Sheffer function if every partial function on Ek is definable in terms of f. Since this holds if and only if f belongs to...
Karsten Schölzel
ISMVL
2009
IEEE
161views Hardware» more  ISMVL 2009»
14 years 5 months ago
Mining Approximative Descriptions of Sets Using Rough Sets
Using concepts from rough set theory we investigate the existence of approximative descriptions of collections of objects that can be extracted from data sets, a problem of intere...
Dan A. Simovici, Selim Mimaroglu
ISMVL
2009
IEEE
189views Hardware» more  ISMVL 2009»
14 years 5 months ago
A Quaternary Decision Diagram Machine and the Optimization of its Code
We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which y...
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura,...
ISMVL
2009
IEEE
124views Hardware» more  ISMVL 2009»
14 years 5 months ago
Equivalence Checking of Reversible Circuits
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits’ primary inputs and outputs must be in pure logic states ...
Robert Wille, Daniel Große, D. Michael Mille...
ISMVL
2009
IEEE
94views Hardware» more  ISMVL 2009»
14 years 5 months ago
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions
This paper proposes a design method for floating-point numerical function generators (NFGs) using multi-valued decision diagrams (MDDs). Our method applies to monotone elementary...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler