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HPCA
1998
IEEE
14 years 20 hour ago
Speculative Versioning Cache
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, G...
HPCA
1998
IEEE
14 years 20 hour ago
Virtual-Physical Registers
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
Antonio González, José Gonzál...
HPCA
1998
IEEE
14 years 20 hour ago
Communication Across Fault-Containment Firewalls on the SGI Origin
Scalability and reliability are inseparable in high-performance computing. Fault-isolation through hardware is a popular means of providing reliability. Unfortunately, such isolat...
Kaushik Ghosh, Allan J. Christie
HPCA
1998
IEEE
14 years 20 hour ago
Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
Scalable shared-memory multiprocessors that are designed as Cache-Only Memory Architectures Coma allow automatic replication and migration of data in the main memory. This enhance...
Sujoy Basu, Josep Torrellas
HPCA
1998
IEEE
14 years 20 hour ago
FPGA Based Custom Computing Machines for Irregular Problems
Over the past few years there has been increased interest in building custom computing machines (CCMs) as a way of achieving very high performance on specific problems. The advent...
David Abramson, Paul Logothetis, Adam Postula, Mar...
HPCA
1998
IEEE
14 years 20 hour ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...
ISHPC
1999
Springer
14 years 20 hour ago
Dynamically Adaptive Parallel Programs
Abstract. Dynamic program optimization is the only recourse for optimizing compilers when machine and program parameters necessary for applying an optimization technique are unknow...
Michael Voss, Rudolf Eigenmann
ISHPC
1999
Springer
14 years 20 hour ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan