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ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
12 years 1 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...
ISCA
2012
IEEE
212views Hardware» more  ISCA 2012»
12 years 1 months ago
TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks
Over the past two decades, several microarchitectural side channels have been exploited to create sophisticated security attacks. Solutions to this problem have mainly focused on ...
Robert Martin, John Demme, Simha Sethumadhavan
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
12 years 1 months ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
12 years 1 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
12 years 1 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
ISCA
2012
IEEE
233views Hardware» more  ISCA 2012»
12 years 1 months ago
iGPU: Exception support and speculative execution on GPUs
Jaikrishnan Menon, Marc de Kruijf, Karthikeyan San...
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
12 years 1 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
12 years 1 months ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
12 years 1 months ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
12 years 1 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar