Sciweavers

ISPASS
2010
IEEE
14 years 6 months ago
Performance-effective operation below Vcc-min
Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been prop...
Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet
ISPASS
2010
IEEE
14 years 6 months ago
The Hadoop distributed filesystem: Balancing portability and performance
—Hadoop is a popular open-source implementation of MapReduce for the analysis of large datasets. To manage storage resources across the cluster, Hadoop uses a distributed user-le...
Jeffrey Shafer, Scott Rixner, Alan L. Cox
ISPASS
2010
IEEE
14 years 6 months ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...
ISPASS
2010
IEEE
14 years 6 months ago
Demystifying GPU microarchitecture through microbenchmarking
—Graphics processors (GPU) offer the promise of more than an order of magnitude speedup over conventional processors for certain non-graphics computations. Because the ften prese...
Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadoo...
ISPASS
2010
IEEE
14 years 6 months ago
Incorporating Instruction-Based Sampling into AMD CodeAnalyst
Paul J. Drongowski, Lei Yu, Frank Swehosky, Surave...
ISPASS
2010
IEEE
14 years 6 months ago
Memphis: Finding and fixing NUMA-related performance problems on multi-core platforms
—Until recently, most high-end scientific applications have been immune to performance problems caused by NonUniform Memory Access (NUMA). However, current trends in micro-proces...
Collin McCurdy, Jeffrey S. Vetter
ISPASS
2010
IEEE
14 years 6 months ago
Dynamic program analysis of Microsoft Windows applications
—Software instrumentation is a powerful and flexible technique for analyzing the dynamic behavior of programs. By inserting extra code in an application, it is possible to study...
Alex Skaletsky, Tevi Devor, Nadav Chachmon, Robert...
ISPASS
2010
IEEE
14 years 6 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
ISPASS
2010
IEEE
14 years 6 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
ISPASS
2010
IEEE
14 years 6 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...