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AHS
2006
IEEE
124views Hardware» more  AHS 2006»
14 years 1 months ago
A Generic On-Chip Debugger for Wireless Sensor Networks
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...
Andrew B. T. Hopkins, Klaus D. McDonald-Maier
AHS
2006
IEEE
148views Hardware» more  AHS 2006»
14 years 1 months ago
Adaptive Micro-Antenna on Silicon Substrate
Adaptive antenna technology represents the most advanced smart antenna approach to date. Using a variety of new signal-processing algorithms, the adaptive system takes advantage o...
Nakul Haridas, Ahmet T. Erdogan, Tughrul Arslan, M...
AHS
2006
IEEE
142views Hardware» more  AHS 2006»
14 years 1 months ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
AHS
2006
IEEE
137views Hardware» more  AHS 2006»
14 years 1 months ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam
AHS
2006
IEEE
86views Hardware» more  AHS 2006»
14 years 1 months ago
An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
AHS
2006
IEEE
124views Hardware» more  AHS 2006»
14 years 1 months ago
Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques
The discrete wavelet Transform (DWT), as defined by the Image Compression Standard JPEG-2000, is one of the most time-consuming computations which cannot be efficiently executed o...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
14 years 1 months ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam
AHS
2006
IEEE
161views Hardware» more  AHS 2006»
14 years 1 months ago
A Self-Tuning Analog Proportional-Integral-Derivative (PID) Controller
We present a framework for a low power self-tuning analog proportional-integral-derivative controller. By using a model-free tuning method, it overcomes problems associated with r...
Varun Aggarwal, Meng Mao, Una-May O'Reilly
AHS
2006
IEEE
109views Hardware» more  AHS 2006»
14 years 1 months ago
VLSI Design IP Protection: Solutions, New Challenges, and Opportunities
It has been a decade since the need of VLSI design intellectual property (IP) protection was identified [1,2]. The goals of IP protection are 1) to enable IP providers to protect ...
Lin Yuan, Gang Qu, Lahouari Ghouti, Ahmed Bouridan...
AHS
2006
IEEE
93views Hardware» more  AHS 2006»
14 years 1 months ago
An FPGA Implemented Processor Architecture with Adaptive Resolution
Reconfigurable software has been applied for a long time. Reconfigurable technology also provides possibility for reconfiguring hardware but this has not been much exploited so...
Jim Torresen, Jonas Jakobsen