Sciweavers

ASPDAC
2008
ACM
82views Hardware» more  ASPDAC 2008»
14 years 2 months ago
Software-cooperative power-efficient heterogeneous multi-core for media processing
Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshi...
ASPDAC
2008
ACM
77views Hardware» more  ASPDAC 2008»
14 years 2 months ago
Parallel fault backtracing for calculation of fault coverage
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jut...
ASPDAC
2008
ACM
99views Hardware» more  ASPDAC 2008»
14 years 2 months ago
A delay model for interconnect trees based on ABCD matrix
- The accuracy of interconnect delay estimations can be improved by the method presented in this paper in which the first two moments are obtained with ABCD matrix and a stable mod...
Guofei Zhou, Li Su, Depeng Jin, Lieguang Zeng
ASPDAC
2008
ACM
73views Hardware» more  ASPDAC 2008»
14 years 2 months ago
Webpage-based benchmarks for mobile device design
Marc Somers, JoAnn M. Paul
ASPDAC
2008
ACM
137views Hardware» more  ASPDAC 2008»
14 years 2 months ago
Automatic interface synthesis based on the classification of interface protocols of IPs
ChangRyul Yun, DongSoo Kang, YoungHwan Bae, Hanhn ...
ASPDAC
2008
ACM
135views Hardware» more  ASPDAC 2008»
14 years 2 months ago
Temperature-aware MPSoC scheduling for reducing hot spots and gradients
Thermal hot spots and temperature gradients on the die need to be minimized to manufacture reliable systems while meeting energy and performance constraints. In this work, we solve...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...
ASPDAC
2008
ACM
95views Hardware» more  ASPDAC 2008»
14 years 2 months ago
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks
A leaf-level clock mesh is known to be very tolerant to variations [1]. However, its use is limited to a few high-end designs because of the high power/resource requirements and la...
Anand Rajaram, David Z. Pan
ASPDAC
2008
ACM
115views Hardware» more  ASPDAC 2008»
14 years 2 months ago
An optimal algorithm for sizing sequential circuits for industrial library based designs
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Che...
ASPDAC
2008
ACM
65views Hardware» more  ASPDAC 2008»
14 years 2 months ago
Statistical noise margin estimation for sub-threshold combinational circuits
Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corpora...
ASPDAC
2008
ACM
80views Hardware» more  ASPDAC 2008»
14 years 2 months ago
An innovative Steiner tree based approach for polygon partitioning
Yongqiang Lu, Qing Su, Jamil Kawa