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    ICMCS
    2005
    IEEE
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    A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
    14 years 5 months ago
    A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
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    The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
    Grzegorz Pastuszak
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