Sciweavers

MEMOCODE
2005
IEEE
14 years 5 months ago
Synthesis of synchronous assertions with guarded atomic actions
The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyu...