CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Software prefetching has been demonstrated as a powerful technique to tolerate long load latencies. However, to be effective, prefetching must target the most critical (frequently...
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Dynamic optimization relies on phase detection for two important functions (1) To detect change in code working set and (2) To detect change in performance characteristics that ca...
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Just-in-time compilers are invoked during application execution and therefore need to ensure fast compilation times. Consequently, runtime compiler designers are averse to impleme...
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Multicluster architectures overcome the scaling problem of centralized resources by distributing the datapath, register file, and memory subsystem across multiple clusters connec...
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
CGO
2006
IEEE
14 years 6 months ago
2006
IEEE
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...