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34
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FPGA
2009
ACM
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FPGA 2009
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Clock power reduction for virtex-5 FPGAs
14 years 6 months ago
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www.eecg.toronto.edu
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson
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