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ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
14 years 5 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...