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ASPDAC
2005
ACM
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ASPDAC 2005
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Clock network minimization methodology based on incremental placement
14 years 5 months ago
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dropzone.tamu.edu
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
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