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129
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ARVLSI
2001
IEEE
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VLSI
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ARVLSI 2001
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A High-Performance 64-bit Adder Implemented in Output Prediction Logic
15 years 6 months ago
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www.csl.cornell.edu
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
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