Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
Sci2ools
International Keyboard
Graphical Social Symbols
CSS3 Style Generator
OCR
Web Page to Image
Web Page to PDF
Merge PDF
Split PDF
Latex Equation Editor
Extract Images from PDF
Convert JPEG to PS
Convert Latex to Word
Convert Word to PDF
Image Converter
PDF Converter
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
29
click to vote
PATMOS
2005
Springer
112
views
Modeling and Simulation
»
more
PATMOS 2005
»
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
14 years 5 months ago
Download
www.eng.auburn.edu
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
claim paper
Read More »