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    ASYNC
    1997
    IEEE
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    On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic
    15 years 20 days ago
    On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic
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    The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...
    Riccardo Mariani, Roberto Roncella, Roberto Salett...
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