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36
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DFT
2007
IEEE
104
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VLSI
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DFT 2007
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Reduction of Fault Latency in Sequential Circuits by using Decomposition
14 years 5 months ago
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www.tau.ac.il
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
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