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DFT
2006
IEEE
125views VLSI» more  DFT 2006»
14 years 5 months ago
Synthesis of Efficient Linear Test Pattern Generators
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
Avijit Dutta, Nur A. Touba
DFT
2006
IEEE
120views VLSI» more  DFT 2006»
14 years 5 months ago
On-Line Mapping of In-Field Defects in Image Sensor Arrays
Continued increase in complexity of digital image sensors means that defects are more likely to develop in the field, but little concrete information is available on in-field defe...
Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapma...
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
14 years 5 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
DFT
2006
IEEE
74views VLSI» more  DFT 2006»
14 years 5 months ago
Recovery Mechanisms for Dual Core Architectures
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic informa...
Christian El Salloum, Andreas Steininger, Peter Tu...