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SIGARCH
2008
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SIGARCH 2008
»
Towards hybrid last level caches for chip-multiprocessors
14 years 11 days ago
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passat.crhc.illinois.edu
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
claim paper
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