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38
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ICCAD
2006
IEEE
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ICCAD 2006
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High-level synthesis challenges and solutions for a dynamically reconfigurable processor
14 years 8 months ago
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www.cecs.uci.edu
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
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