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    ETS
    2007
    IEEE
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    An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
    14 years 5 months ago
    An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
    Download  www.date.uni-paderborn.de
    An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
    Philipp Öhler, Sybille Hellebrand, Hans-Joach...
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