In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent yea...
Recent years have seen a proliferation of 3-valued or capturing abstractions of systems, since these enable verifying both universal and existential properties. Reasoning about suc...
We formally define--at the stream transformer level--a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properti...
Sava Krstic, Jordi Cortadella, Michael Kishinevsky...
The last few years have seen the advent of a new breed of decision procedures for various fragments of first-order logic based on ional abstraction. A lazy satisfiability checker ...
We introduce a finer concept of a Hardware Machine, where the set of post-reboot operation states is explicitly a part of the FSM definition. We formalize an ad-hoc flow of combin...
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Z...
We present an approach to automatic synthesis of specifications given in Linear Time Logic. The approach is based on a translation through universal co-B
In this paper, a new heuristic-based approach is introduced to extract minimally unsatisfiable subformulas (in short, MUSes) of SAT instances. It is shown that it often outperforms...