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FMCAD
2007
Springer
14 years 4 months ago
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs
Abstract--Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recentl...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...
FMCAD
2007
Springer
14 years 4 months ago
Improved Design Debugging Using Maximum Satisfiability
In today's SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sourc...
Sean Safarpour, Hratch Mangassarian, Andreas G. Ve...
FMCAD
2007
Springer
14 years 4 months ago
A Mechanized Refinement Framework for Analysis of Custom Memories
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
Sandip Ray, Jayanta Bhadra
FMCAD
2007
Springer
14 years 4 months ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet
FMCAD
2007
Springer
14 years 4 months ago
Boosting Verification by Automatic Tuning of Decision Procedures
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
Frank Hutter, Domagoj Babic, Holger H. Hoos, Alan ...
FMCAD
2007
Springer
14 years 4 months ago
Transaction Based Modeling and Verification of Hardware Protocols
Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior ...
Xiaofang Chen, Steven M. German, Ganesh Gopalakris...
FMCAD
2007
Springer
14 years 6 months ago
Induction in CEGAR for Detecting Counterexamples
— Induction has been studied in model checking for proving the validity of safety properties, i.e., showing the absence of counterexamples. To our knowledge, induction has not be...
Chao Wang, Aarti Gupta, Franjo Ivancic
FMCAD
2007
Springer
14 years 6 months ago
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC
—When model-checking reports that a property holds on a model, vacuity detection increases user confidence in this result by checking that the property is satisfied in the inte...
Jocelyn Simmonds, Jessica Davies, Arie Gurfinkel, ...
FMCAD
2007
Springer
14 years 6 months ago
What Triggers a Behavior?
Orna Kupferman, Yoad Lustig
FMCAD
2007
Springer
14 years 6 months ago
Fast Minimum-Register Retiming via Binary Maximum-Flow
We present a formulation of retiming to minimize the number of registers in a design by iterating a maximum network flow problem. The retiming returned will be the optimum one whi...
Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton