FMSD
2000
13 years 10 months ago
2000
FMSD
2000
13 years 10 months ago
2000
We review a number of formal verification techniques supported by STeP, the Stanford Temporal Prover, describing how the tool can be used to verify properties of several versions o...
FMSD
2000
13 years 10 months ago
2000
The study of asynchronous circuit behaviors in the presence of component and wire delays has received a great deal of attention. In this paper, we consider asynchronous circuits wh...