This paper presents experiments realized by Airbus on model checking a safety critical system, lessons learnt and ways forward to extend the industrial use of formal verification ...
Formal verification efforts in the area of robotics are still comparatively scarce. In this paper we report on our experiences with one such effort, which was concerned with design...
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
straction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to ifications to be verified....
Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of reali...
Robert P. Kurshan, Vladimir Levin, Marius Minea, D...
This article describes the formal verification of a compilation algorithm that transforms parallel moves (parallel assignments between variables) into a semanticallyequivalent sequ...
Laurence Rideau, Bernard P. Serpette, Xavier Leroy
The approaches to automatic formal verification of UML models known up to now require a finite bound on the number of objects existing at each point in time. In [4] we have observ...
The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases...
Chris J. Myers, Reid R. Harrison, David Walter, Ni...
Reusable software components need well-defined interfaces, rigorously and completely documented features, and a design amenable both to reuse and to formal verification; all these...
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...