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EURODAC
1995
IEEE
142views VHDL» more  EURODAC 1995»
14 years 4 months ago
Creating hierarchy in HDL-based high density FGPA design
As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (HDLs) is rapidly supplanting schematic entry ...
Carol A. Fields