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HPCA
2004
IEEE
14 years 9 months ago
Exploring Wakeup-Free Instruction Scheduling
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwi...
HPCA
2004
IEEE
14 years 9 months ago
Improving Disk Throughput in Data-Intensive Servers
Low disk throughput is one of the main impediments to improving the performance of data-intensive servers. In this paper, we propose two management techniques for the disk control...
Enrique V. Carrera, Ricardo Bianchini
HPCA
2004
IEEE
14 years 9 months ago
Program Counter Based Techniques for Dynamic Power Management
Reducing energy consumption has become one of the major challenges in designing future computing systems. This paper proposes a novel idea of using program counters to predict I/O...
Chris Gniady, Y. Charlie Hu, Yung-Hsiang Lu
HPCA
2004
IEEE
14 years 9 months ago
Reducing Branch Misprediction Penalty via Selective Branch Recovery
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...
Amit Gandhi, Haitham Akkary, Srikanth T. Srinivasa...
HPCA
2004
IEEE
14 years 9 months ago
Perceptron-Based Branch Confidence Estimation
Pipeline gating has been proposed for reducing wasted speculative execution due to branch mispredictions. As processors become deeper or wider, pipeline gating becomes more import...
Haitham Akkary, Srikanth T. Srinivasan, Rajendar K...
HPCA
2004
IEEE
14 years 9 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
Todd E. Ehrhart, Sanjay J. Patel
HPCA
2004
IEEE
14 years 9 months ago
Hardware Support for Prescient Instruction Prefetch
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wan...