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    Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
    13 years 11 months ago
    Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
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    Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
    Yu Hu, Victor Shih, Rupak Majumdar, Lei He
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