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    ISCA
    2002
    IEEE
    108views Hardware» more  ISCA 2002»
    A Scalable Instruction Queue Design Using Dependence Chains
    14 years 10 months ago
    A Scalable Instruction Queue Design Using Dependence Chains
    Download  www.eecs.umich.edu
    Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
    Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
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    GLVLSI
    2005
    IEEE
    152views VLSI» more  GLVLSI 2005»
    Increasing design space of the instruction queue with tag coding
    14 years 11 months ago
    Increasing design space of the instruction queue with tag coding
    Download  www.egr.msu.edu
    The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
    Junwei Zhou, Andrew Mason
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