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    VLSID
    2007
    IEEE
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    An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
    14 years 12 months ago
    An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
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    With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
    Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...
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