Sciweavers

ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
14 years 5 months ago
Matrix scheduler reloaded
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, ...