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    ICCAD
    2006
    IEEE
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    Soft error reduction in combinational logic using gate resizing and flipflop selection
    14 years 8 months ago
    Soft error reduction in combinational logic using gate resizing and flipflop selection
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    Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
    Rajeev R. Rao, David Blaauw, Dennis Sylvester
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