Several efficient compilation techniques have been recently proposed for the generation of sequential (C) code from Esterel programs. Consisting essentially in direct simulation ...
An executable computational logic can provide the desired bridge between formal system properties and formal methods to verify them on the one hand, and executable models of syste...
— Modern SAT solvers have proved highly successful in finding counterexamples to temporal properties of systems, using a method known as ”bounded model checking”. It is natu...
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Formal techniques have been widely applied in the design of real-time systems and have significantly helped detect design errors by checking real-time properties of the model. Ho...
CSP (Communicating Sequential Processes) is a useful algebraic notation for creating a hierarchical behavioural specification for concurrent systems, due to its formal interproces...
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
In this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into...