MEMOCODE
2005
IEEE
14 years 6 months ago
2005
IEEE
The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
MEMOCODE
2005
IEEE
14 years 6 months ago
2005
IEEE
This paper presents results on processor specification from a specialized high-level finite state machine (FSM) language. The language is an extension and enhancement of earlier...
MEMOCODE
2005
IEEE
14 years 6 months ago
2005
IEEE
We recall the story of the development of the synchronous data-flow language LUSTRE and of its industrial transfer inside the toolset SCADE. We try to analyse the reasons of its ...
MEMOCODE
2005
IEEE
14 years 6 months ago
2005
IEEE
MEMOCODE
2005
IEEE
14 years 6 months ago
2005
IEEE
There are few published examples of the proof of correctness of a cache-coherence protocol expressed in an HDL. A designer generally shows the correctness of a protocol ny impleme...
MEMOCODE
2005
IEEE
14 years 6 months ago
2005
IEEE
In principle, bounded model checking (BMC) leads to semidecision procedures that can be used to verify liveness properties and to falsify safety properties. If the procedures fail...
MEMOCODE
2005
IEEE
14 years 6 months ago
2005
IEEE
We describe race-free properties of a hardware description language called GEZEL. The language describes networks of cycle-true finite-state-machines with datapaths (FSMDs). We de...