MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
Numerical applications frequently contain nested loop structures that process large arrays of data. The execution of these loop structures often produces memory preference pattern...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
Branch instructions are recognized as a major impediment to exploiting instruction level parallelism. Even with sophisticated branch prediction techniques, many frequently execute...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
: Program profiles identify frequently executed portions of a program, which are the places at which optimizations offer programmers and compilers the greatest benefit. Compilers, ...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
We examine two pipeline structures which are employed in commercial microprocessors. The first is the load-use interlock (LUI) pipeline, which employs an interlock to ensure corre...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
MICRO
1994
IEEE
14 years 4 months ago
1994
IEEE