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    ASPDAC
    2006
    ACM
    103views Hardware» more  ASPDAC 2006»
    Low area pipelined circuits by multi-clock cycle paths and clock scheduling
    14 years 24 days ago
    Low area pipelined circuits by multi-clock cycle paths and clock scheduling
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    — A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
    Bakhtiar Affendi Rosdi, Atsushi Takahashi
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