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DFT
2007
IEEE
112views VLSI» more  DFT 2007»
14 years 5 months ago
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model
During semiconductor manufacturing, particles undesirably depose on the surface of the wafer causing “open” and “short” defects to interconnects. In this paper, a third ty...
Rani S. Ghaida, Payman Zarkesh-Ha