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    IFIP
    1993
    Springer
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    Self-Timed Architecture of a Reduced Instruction Set Computer
    14 years 8 months ago
    Self-Timed Architecture of a Reduced Instruction Set Computer
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    An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
    Ilana David, Ran Ginosar, Michael Yoeli
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