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ISCAS
2008
IEEE
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14 years 1 months ago
A dual-core programmable decoder for LDPC convolutional codes
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
Marcos B. S. Tavares, Emil Matús, Steffen K...