We consider a system of compute and storage resources geographically distributed over a large number of locations connected via a wide-area network. By distributing the resources,...
Moritz Steiner, Bob Gaglianello Gaglianello, Vijay...
Abstract. Few of the benefits of exploiting partially reconfigurable devices are power consumption reduction, cost reduction, and customized performance improvement. To obtain thes...
Thomas Marconi, Yi Lu 0004, Koen Bertels, Georgi G...
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
— Typically, placement algorithms attempt to minimize the total net length of a printed circuit board (PCB). However, an MCM’s increased throughput and dense circuitry can easi...
This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first ...
Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tu...
Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates ...
Abstract— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness...
I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David...
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
Automatic circuit placement has received renewed interest recently given the rapid increase of circuit complexity, increase of interconnect delay, and potential sub-optimality of ...