Sciweavers

DSD
2007
IEEE
132views Hardware» more  DSD 2007»
14 years 4 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge