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35
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DSD
2007
IEEE
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DSD 2007
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On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
14 years 4 months ago
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www.dave-roberts.me.uk
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge
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