On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...
Compilers use register coalescing to avoid generating code for copy instructions. For architectures with register aliasing such as x86, Smith, Ramsey, and Holloway (2004) presented...
Abstract. This paper deals with coalescing in SSA-based register allocation. Current coalescing techniques all require the interference graph to be built. This is generally conside...
Abstract. Scientists are increasingly using dynamic programming languages like Matlab for prototyping and implementation. Effectively compiling Matlab raises many challenges due t...
Maxime Chevalier-Boisvert, Laurie J. Hendren, Clar...
Abstract. Following the translation validation approach to highassurance compilation, we describe a new algorithm for validating a posteriori the results of a run of register alloc...
Implementing the 23 Gang-of-Four design patterns in the aspectoriented programming language Object Teams/Java (OT/J) yields modularity and reusability results roughly comparable t...
A fully automatic, compiler-driven approach to parallelisation can result in unpredictable time and space costs for compiled code. On the other hand, a fully manual approach to pa...
Message-passing is an attractive thread coordination mechanism because it cleanly delineates points in an execution when threads communicate, and unifies synchronization and comm...
K. C. Sivaramakrishnan, Lukasz Ziarek, Raghavendra...
We propose a programming paradigm called compress-and-conquer (CC) that leads to optimal performance on multicore platforms. Given a multicore system of p cores and a problem of s...