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43
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DAC
2007
ACM
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Computer Architecture
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DAC 2007
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Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
14 years 12 months ago
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cobweb.ecn.purdue.edu
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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