Even though the well-known nested-depth first search algorithm for LTL model checking provides good performance, it cannot benefit from the recent advent of multi-core computers....
In this paper, we present RAMBO, an algorithm for emulating a read/write distributed shared memory in a dynamic, rapidly changing environment. RAMBO provides a highly reliable, hi...
Seth Gilbert, Nancy A. Lynch, Alexander A. Shvarts...
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
While clusters of commodity servers and switches are the most popular form of large-scale parallel computers, many programs are not easily parallelized for execution upon them. In...
Hanjun Kim, Arun Raman, Feng Liu, Jae W. Lee, Davi...
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
A major trend in HPC is the escalation toward manycore, where systems are composed of shared memory nodes featuring numerous processing units. Unfortunately, with scale comes compl...
Teng Ma, George Bosilca, Aurelien Bouteiller, Jack...
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...
provide tools or abstractions that allow developers to program in parallel. But what hardware do we need to support shared memory threads? The hardware should provide a well-defin...
Motivated by experience gained during the validation of a recent Approximate Mean Value Analysis (AMVA) model of modern shared memory architectures, this paper re-examines the &qu...