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ETS
2010
IEEE
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ETS 2010
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Test-architecture optimization for TSV-based 3D stacked ICs
14 years 1 months ago
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people.ee.duke.edu
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
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